Meanwhile, most instructions are implemented, some are still missing though.
At the moment, I implement the Instruction Cache
Because the DSP 56362 that is used in the Powercore (Firewire) allows access to the instruction cache through P-memory, the instruction cache has to be emulated aswell.
That’s something I didn’t plan to do, the plock/pfree and other cache instructions are currently left empty because I thought I didn’t have to implement them. Well, things have changed, so they will be implemented properly and the instruction cache, too.
Stay tuned….